[subexp-daq] Strange instability of the event counter register of the CAEN V767 module

[Weber, Guenter Dr.]

Dear friends,


we just noticed that the value that is read from the event counter register (Base + %004C) of V767 is not stable during times when the module does internal operations. To demonstrate this we used the following code:

last_event_counter = MAP_READ(caen_v767a->sicy_map, event_counter);
write_op(caen_v767a->sicy_map, 0x1000); /* set mode of operation */
t = time_getd();
while ( last_event_counter != MAP_READ(caen_v767a->sicy_map, event_counter) )
{
    usleep(1);
}
t = time_getd() - t;
LOGF(info)(LOGL, NAME" TIME is %f", t);

last_event_counter = MAP_READ(caen_v767a->sicy_map, event_counter);
window_setting = config_get_int32(caen_v767a->module.config, KW_WIDTH, CONFIG_UNIT_NONE, 0x0001, 0x84D0);
write_op(caen_v767a->sicy_map, 0x3000); /* set time window length */
write_op(caen_v767a->sicy_map, window_setting);
t = time_getd();
while ( last_event_counter != MAP_READ(caen_v767a->sicy_map, event_counter) )
{
    usleep(1);
}
t = time_getd() - t;
LOGF(info)(LOGL, NAME" TIME is %f", t);

last_event_counter = MAP_READ(caen_v767a->sicy_map, event_counter);
window_setting = config_get_int32(caen_v767a->module.config, KW_OFFSET, CONFIG_UNIT_NONE, 1 - 320000, window_setting + 2000 - 1);
write_op(caen_v767a->sicy_map, 0x3200); /* set time window offset */
write_op(caen_v767a->sicy_map, window_setting);
t = time_getd();
while ( last_event_counter != MAP_READ(caen_v767a->sicy_map, event_counter) )
{
    usleep(1);
}
t = time_getd() - t;
LOGF(info)(LOGL, NAME" TIME is %f", t);

last_event_counter = MAP_READ(caen_v767a->sicy_map, event_counter);
write_op(caen_v767a->sicy_map, 0x7000); /* set data ready status to event ready */
t = time_getd();
while ( last_event_counter != MAP_READ(caen_v767a->sicy_map, event_counter) )
{
    usleep(1);
}
t = time_getd() - t;
LOGF(info)(LOGL, NAME" TIME is %f", t);


And the output in two trials was the following:


10: module/caen_v767a/caen_v767a.c:143: ..CEAN_V767A TIME is 0.000002
10: module/caen_v767a/caen_v767a.c:155: ..CEAN_V767A TIME is 0.000002
10: module/caen_v767a/caen_v767a.c:167: ..CEAN_V767A TIME is 0.055224
10: module/caen_v767a/caen_v767a.c:177: ..CEAN_V767A TIME is 0.000354


10: module/caen_v767a/caen_v767a.c:143: ....CEAN_V767A TIME is 0.000002
10: module/caen_v767a/caen_v767a.c:155: ....CEAN_V767A TIME is 0.000002
10: module/caen_v767a/caen_v767a.c:167: ....CEAN_V767A TIME is 0.055223
10: module/caen_v767a/caen_v767a.c:177: ....CEAN_V767A TIME is 0.000387


Thus, we can conclude that the event counter register is set to some fake value for up to almost 60 ms as a result of an internal operation of the module. Only after this time, the register goes back to the real value.


We will now take care of this effect and after each WRITE_OP call wait for the event counter to to gack to the original value. However, who knows what happens in the other registers of the module (and for how long).


As the event counter value is used as a sanity check in CRATE.C it might make sense to check if some of the other CAEN modules also exhibit this 'fascinating feature'.





Best greetings

Günter


-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.chalmers.se/pipermail/subexp-daq/attachments/20240301/11763e88/attachment.html>