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<p>Dear friends,</p>
<p><br>
</p>
<p>we just noticed that the value that is read from the event counter register (<span>Base + %004C</span>) of V767 is not stable during times when the module does internal operations. To demonstrate this we used the following code:</p>
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<div><span style="font-size: 8pt;">last_event_counter = MAP_READ(caen_v767a->sicy_map, event_counter);</span><br>
<span style="font-size: 8pt;">write_op(caen_v767a->sicy_map, 0x1000); /* set mode of operation */</span><br>
<span style="font-size: 8pt;">t = time_getd();</span><br>
<span style="font-size: 8pt;">while ( last_event_counter != MAP_READ(caen_v767a->sicy_map, event_counter) )
</span><br>
<span style="font-size: 8pt;">{</span><br>
<span style="font-size: 8pt;"> usleep(1);</span><br>
<span style="font-size: 8pt;">}</span><br>
<span style="font-size: 8pt;">t = time_getd() - t;</span><br>
<span style="font-size: 8pt;">LOGF(info)(LOGL, NAME" TIME is %f", t);</span><br>
<br>
<span style="font-size: 8pt;">last_event_counter = MAP_READ(caen_v767a->sicy_map, event_counter);</span><br>
<span style="font-size: 8pt;">window_setting = config_get_int32(caen_v767a->module.config, KW_WIDTH, CONFIG_UNIT_NONE, 0x0001, 0x84D0);</span><br>
<span style="font-size: 8pt;">write_op(caen_v767a->sicy_map, 0x3000); /* set time window length */</span><br>
<span style="font-size: 8pt;">write_op(caen_v767a->sicy_map, window_setting);</span><br>
<span style="font-size: 8pt;">t = time_getd();</span><br>
<span style="font-size: 8pt;">while ( last_event_counter != MAP_READ(caen_v767a->sicy_map, event_counter) )
</span><br>
<span style="font-size: 8pt;">{</span><br>
<span style="font-size: 8pt;"> usleep(1);</span><br>
<span style="font-size: 8pt;">}</span><br>
<span style="font-size: 8pt;">t = time_getd() - t;</span><br>
<span style="font-size: 8pt;">LOGF(info)(LOGL, NAME" TIME is %f", t);</span><br>
<br>
<span style="font-size: 8pt;">last_event_counter = MAP_READ(caen_v767a->sicy_map, event_counter);</span><br>
<span style="font-size: 8pt;">window_setting = config_get_int32(caen_v767a->module.config, KW_OFFSET, CONFIG_UNIT_NONE, 1 - 320000, window_setting + 2000 - 1);</span><br>
<span style="font-size: 8pt;">write_op(caen_v767a->sicy_map, 0x3200); /* set time window offset */</span><br>
<span style="font-size: 8pt;">write_op(caen_v767a->sicy_map, window_setting);</span><br>
<span style="font-size: 8pt;">t = time_getd();</span><br>
<span style="font-size: 8pt;">while ( last_event_counter != MAP_READ(caen_v767a->sicy_map, event_counter) )
</span><br>
<span style="font-size: 8pt;">{</span><br>
<span style="font-size: 8pt;"> usleep(1);</span><br>
<span style="font-size: 8pt;">}</span><br>
<span style="font-size: 8pt;">t = time_getd() - t;</span><br>
<span style="font-size: 8pt;">LOGF(info)(LOGL, NAME" TIME is %f", t);</span><br>
<br>
<span style="font-size: 8pt;">last_event_counter = MAP_READ(caen_v767a->sicy_map, event_counter);</span><br>
<span style="font-size: 8pt;">write_op(caen_v767a->sicy_map, 0x7000); /* set data ready status to event ready */</span><br>
<span style="font-size: 8pt;">t = time_getd();</span><br>
<span style="font-size: 8pt;">while ( last_event_counter != MAP_READ(caen_v767a->sicy_map, event_counter) )
</span><br>
<span style="font-size: 8pt;">{</span><br>
<span style="font-size: 8pt;"> usleep(1);</span><br>
<span style="font-size: 8pt;">}</span><br>
<span style="font-size: 8pt;">t = time_getd() - t;</span><br>
<span style="font-size: 8pt;">LOGF(info)(LOGL, NAME" TIME is %f", t); </span><br>
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<p>And the output in two trials was the following:</p>
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<div><span style="font-size: 8pt;">10: module/caen_v767a/caen_v767a.c:143: ..CEAN_V767A TIME is 0.000002</span><br>
<span style="font-size: 8pt;">10: module/caen_v767a/caen_v767a.c:155: ..CEAN_V767A TIME is 0.000002</span><br>
<span style="font-size: 8pt;">10: module/caen_v767a/caen_v767a.c:167: ..CEAN_V767A TIME is 0.055224</span><br>
<span style="font-size: 8pt;">10: module/caen_v767a/caen_v767a.c:177: ..CEAN_V767A TIME is 0.000354</span></div>
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<p></p>
<div><span style="font-size: 8pt;"><span>10: module/caen_v767a/caen_v767a.c:143: ....CEAN_V767A TIME is 0.000002</span><br>
</span></div>
<div><span style="font-size: 8pt;">10: module/caen_v767a/caen_v767a.c:155: ....CEAN_V767A TIME is 0.000002</span><br>
<span style="font-size: 8pt;">10: module/caen_v767a/caen_v767a.c:167: ....CEAN_V767A TIME is 0.055223</span><br>
<span style="font-size: 8pt;">10: module/caen_v767a/caen_v767a.c:177: ....CEAN_V767A TIME is 0.000387</span></div>
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<p>Thus, we can conclude that the event counter register is set to some fake value for up to almost 60 ms as a result of an internal operation of the module. Only after this time, the register goes back to the real value.</p>
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<p>We will now take care of this effect and after each WRITE_OP call wait for the event counter to to gack to the original value. However, who knows what happens in the other registers of the module (and for how long).</p>
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<p>As the event counter value is used as a sanity check in CRATE.C it might make sense to check if some of the other CAEN modules also exhibit this 'fascinating feature'.</p>
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<p>Best greetings</p>
<p>Günter<br>
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