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<p>Dear friends,</p>
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<p>in the merged SIS3316 code we found RATACLOCK, which does not exist (at least not under this name) in the module interface that we took over from Bastian. I also cannot find RATACLOCK in the manual from STRUCK.</p>
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<p>For a bunch of firmware versions it is hardcoded that HAS_RATACLOCK_RECEIVER is true.</p>
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<p></p>
<div><span style="font-size: 10pt;"> if (firmware == 0x33165010 || firmware == 0x3316b011</span><br>
<span style="font-size: 10pt;"> || firmware == 0x3316a012 || firmware == 0x3316b012) {</span><br>
<span style="font-size: 10pt;"> m->config.has_rataclock_receiver = 1;</span><br>
<span style="font-size: 10pt;"> }</span></div>
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<p>It happens that one of our modules has indeed firmware version <span>0x3316a012</span>. So, this variable is set to true. This results in the following check:</p>
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<div><span style="font-size: 10pt;">void</span><br>
<span style="font-size: 10pt;">sis_3316_test_clock_sync(struct Sis3316Module *self)</span><br>
<span style="font-size: 10pt;">{</span><br>
<span style="font-size: 10pt;"> /* test, if all clocks are still synced */</span><br>
<span style="font-size: 10pt;"> if (self->config.has_rataclock_receiver == 1) {</span><br>
<span style="font-size: 10pt;"> int tries_left = 3;</span><br>
<span style="font-size: 10pt;"> int ok = 1;</span><br>
<br>
<span style="font-size: 10pt;"> while (tries_left > 0) {</span><br>
<span style="font-size: 10pt;"> int i;</span><br>
<br>
<span style="font-size: 10pt;"> for (i = 0; i < N_ADCS; ++i) {</span><br>
<span style="font-size: 10pt;"> uint32_t status = MAP_READ(self->sicy_map,</span><br>
<span style="font-size: 10pt;"> fpga_adc_rataser_status1(i));</span><br>
<span style="font-size: 10pt;"> int sync = status & 0x7;</span><br>
<span style="font-size: 10pt;"> int lost = (status >> 4) & 0x7;</span><br>
<span style="font-size: 10pt;"> int auto_edge =</span><br>
<span style="font-size: 10pt;"> self->config.rataclock_use_auto_edge;</span><br>
<span style="font-size: 10pt;"> if (sync != 7) {</span><br>
<span style="font-size: 10pt;"> log_error(LOGL, NAME</span><br>
<span style="font-size: 10pt;"> " ADC%d clock not synced "</span><br>
<span style="font-size: 10pt;"> "(sync = %d) "</span><br>
<span style="font-size: 10pt;"> "(tries_left = %d)", i, sync,</span><br>
<span style="font-size: 10pt;"> tries_left);</span><br>
<span style="font-size: 10pt;"> ok = 0;</span><br>
<span style="font-size: 10pt;"> }</span><br>
<span style="font-size: 10pt;"> if (lost != 0) {</span><br>
<span style="font-size: 10pt;"> log_error(LOGL, NAME</span><br>
<span style="font-size: 10pt;"> " ADC%d clock lost sync"</span><br>
<span style="font-size: 10pt;"> "(lost = %d)", i, lost);</span><br>
<span style="font-size: 10pt;"> ok = 0;</span><br>
<span style="font-size: 10pt;"> MAP_WRITE(self->sicy_map,</span><br>
<span style="font-size: 10pt;"> fpga_adc_rataser_control2(i),</span><br>
<span style="font-size: 10pt;"> (1 << 31) | (auto_edge << 2));</span><br>
<br>
<span style="font-size: 10pt;"> }</span><br>
<span style="font-size: 10pt;"> }</span><br>
<span style="font-size: 10pt;"> if (ok == 0) {</span><br>
<span style="font-size: 10pt;"> tries_left -= 1;</span><br>
<span style="font-size: 10pt;"> time_sleep(1e-3);</span><br>
<span style="font-size: 10pt;"> } else {</span><br>
<span style="font-size: 10pt;"> LOGF(debug)(LOGL, "rataser clock synced.");</span><br>
<span style="font-size: 10pt;"> break;</span><br>
<span style="font-size: 10pt;"> }</span><br>
<span style="font-size: 10pt;"> MAP_WRITE(self->sicy_map, reset_adc_clock, 0x0);</span><br>
<span style="font-size: 10pt;"> time_sleep(30e-3);</span><br>
<span style="font-size: 10pt;"> }</span><br>
<span style="font-size: 10pt;"> }</span><br>
<span style="font-size: 10pt;">}</span></div>
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<p>And we receive an error message that our ADCs are not synchronized. As I have no idea what RATACLOCK is, it is hard for me to figure out what is happening.</p>
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<p><span style="font-size: 14pt;">However, there is also the parameter USE_RATACLOCK. It is set to 0 by default. So, maybe it is simply a bug that the check for synchronization is executed just on the basis of
</span><span style="font-size: 14pt;">if (self->config.has_rataclock_receiver == 1)</span><span style="font-size: 14pt;">, while</span><span style="font-size: 14pt;"> not also checking for
</span><span style="font-size: 10pt;"><span style="font-size: 14pt;">if (self->config.use</span><span style="font-size: 14pt;">_rataclock</span><span style="font-size: 14pt;"> == 1)</span></span><span style="font-size: 14pt;">?</span></p>
<p><span style="font-size: 14pt;">But shouldn't the expectation be that the ADCs are always synchronized? So, maybe this is still a problem with the configuration of our module?</span></p>
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</span></p>
<p><span style="font-size: 14pt;">Sorry for this confusion. I would really appreciate if someone could explain what is going on here
<span>😊</span><br>
</span></p>
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</span></p>
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</span></p>
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</span></p>
<p><span style="font-size: 14pt;">Best greetings from Jena</span></p>
<p><span style="font-size: 14pt;">Günter<br>
</span></p>
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