log_level=verbose # info, verbose, debug, spam CRATE("MCAL") { GSI_VULOM(0x03000000) { timestamp = true # needed to get timestamps in the data output } GSI_VETAR(0x50000000) { } BARRIER SIS_3316(0x30000000) { clk_freq = 125 MHz ext_clk_freq = 12 MHz # expects 12.5 MHz from VULOM tap_delay_fine_tune = 0 # [-32..32] * 40 ps use_external_trigger = 0..15 channels_to_read = () # Which channels contribute to TO signal (OR-ed) # by default, all are contributing # Enable only ch0: 0x0001, ch1: 0x0002, ch2: 0x0004, ch3: 0x0008 trigger_output = () use_maw3 = false use_maxe = true range = 5V use_termination = false blt_mode = blt_2esst signal_decaytime = (2000 ns {16}) # trigger filter integration & differentiation peak = (510 {16}) gap = (510 {16}) # energy filter integration & differentiation peak_e = (500 {16}) gap_e = (500 {16}) threshold = (8mV, 8mV, 8mV, 15mV, 8mV, 8mV, 10mV, 8mV, 8mV, 8mV, 13mV, 8mV, 8mV, 8mV, 8mV, 15mV) offset = (0 {16}) # -0x8000 .. 0x80000 average_mode = (16 {4}) average_pretrigger = (3900 {4}) average_length = (16384 {4}) write_traces_raw = false use_dual_threshold = 0..15 # discard_data = 0..15 # discard_threshold = 0 TRACES(raw) { sample_length = (8 us {4}) pretrigger_delay = (32500 ns {4}) } # Gates are distributed evenly across a 65536 sample range # Each gate has the maximum width of 4096 ns = 512 samples # This samples the signal with a low-resolution trace. use_accumulator2 = true use_accumulator6 = true GATE(0) { time_after_trigger = 1024 ns width = 2048 ns } GATE(1) { time_after_trigger = 65000 ns width = 4096 ns } GATE(2) { time_after_trigger = 130000 ns width = 4096 ns } GATE(3) { time_after_trigger = 195000 ns width = 4096 ns } GATE(4) { time_after_trigger = 260000 ns width = 4096 ns } GATE(5) { time_after_trigger = 325000 ns width = 4096 ns } GATE(6) { time_after_trigger = 390000 ns width = 4096 ns } GATE(7) { time_after_trigger = 455000 ns width = 4096 ns } #use_dithering = true } SIS_3316(0x31000000) { is_fpbus_master = false clk_freq = 125 MHz use_external_trigger = 0..15 channels_to_read = 0..15 trigger_output = () #0..15 use_maw3 = false use_maxe = true range = 5V use_termination = false blt_mode = blt_2esst signal_decaytime = (2000 ns {16}) # trigger filter integration & differentiation peak = (510 {16}) gap = (510 {16}) # energy filter integration & differentiation peak_e = (500 {16}) gap_e = (500 {16}) threshold = (10mV, 8mV, 8mV, 8mV, 8mV, 10mV, 13mV, 8mV, 8mV, 8mV, 8mV, 8mV, 8mV, 8mV, 8mV, 8mV) offset = (0 {16}) # -0x8000 .. 0x80000 average_mode = (16 {4}) average_pretrigger = (3900 {4}) average_length = (16384 {4}) write_traces_raw = false use_dual_threshold = 0..15 #discard_data = 0..15 #discard_threshold = 0 TRACES(raw) { sample_length = (8 us {4}) pretrigger_delay = (32500 ns {4}) } use_accumulator2 = true use_accumulator6 = true GATE(0) { time_after_trigger = 1024 ns width = 2048 ns } GATE(1) { time_after_trigger = 65000 ns width = 4096 ns } GATE(2) { time_after_trigger = 130000 ns width = 4096 ns } GATE(3) { time_after_trigger = 195000 ns width = 4096 ns } GATE(4) { time_after_trigger = 260000 ns width = 4096 ns } GATE(5) { time_after_trigger = 325000 ns width = 4096 ns } GATE(6) { time_after_trigger = 390000 ns width = 4096 ns } GATE(7) { time_after_trigger = 455000 ns width = 4096 ns } } # SIS_3316(0x32000000) { # is_fpbus_master = false # clk_freq = 125 MHz # use_external_trigger = 0 # channels_to_read = 0 # trigger_output = () # use_maw3 = false # use_maxe = true # range = 5V # use_termination = true # blt_mode = blt_2esst # signal_decaytime = (2000 ns {16}) # # trigger filter integration & differentiation # peak = (510 {16}) # gap = (510 {16}) # # energy filter integration & differentiation # peak_e = (500 {16}) # gap_e = (500 {16}) # threshold = (20mV, 20mV, 22mV, 22mV, # 20mV, 20mV, 20mV, 20mV, # 20mV, 20mV, 20mV, 20mV, # 20mV, 20mV, 20mV, 20mV) # offset = (0 {16}) # -0x8000 .. 0x80000 # average_mode = (4 {4}) # average_pretrigger = (4094 {4}) # average_length = (16384 {4}) # write_traces_raw = true # use_dual_threshold = 0..15 # TRACES(raw) { # sample_length = (8000 us {4}) # pretrigger_delay = (0 us {4}) # } # discard_data = 1..15 # discard_threshold = 0 # } }