/* vim: set filetype=cpp: */

/*
 * This setup is for the sis3316 (Struck ADC)
 *
 * ECL_IN 1-5 <- trigger output of sis 0-4
 * ECL_OUT 1-5 -> trigger input of sis 0-4
 * ECL_OUT 7-8 -> pulser going to channel 1 of all sis modules (via fanout module)
 * LEMO_OUT 1 -> clock signal to CI on first sis module (12.5 MHz)
 * LEMO_OUT 2 -> clock signal for scope, compare with sis module CO signal
 */

SECTION(module_trigger)
{
	all_or_mask(1) = ECL_IN(1) | ECL_IN(2) | ECL_IN(3) | ECL_IN(4) | ECL_IN(5);
	TRIG_LMU_AUX(1) = ALL_OR(1);
	TRIG_LMU_OUT(1) = TRIG_LMU_AUX(1);
}

SECTION(pulser_trigger)
{
	period(4) = 1000 ms;	
	TRIG_LMU_AUX(1) = PULSER(4);	
	TRIG_LMU_OUT(1) = TRIG_LMU_AUX(1);	
}

SECTION(pulser_to_channels)
{
	/* Pulser for channels */
	period(1) = 100 us;
	GATE_DELAY(1) = PULSER(1);
	stretch(1) = 100 ns;
	ECL_OUT(7) = GATE_DELAY(1);
	ECL_OUT(8) = GATE_DELAY(1);
}

SECTION(standalone)
{
	FRONT_LED(1) = ECL_IO_IN(4);
	FRONT_LED(2) = MASTER_START;
	FRONT_LED(3) = ACCEPT_PULSE;

	/* Deadtime is received from TRIMI. */
	/* DEADTIME_IN(1) = TRIMI_TDT; */

	/* Deadtime is received from TRIVA. */
	DEADTIME_IN(1) = ECL_IO_IN(4);

	/* Encoded trigger is sent to TRIVA. */
	ECL_IO_OUT(1) = ENCODED_TRIG(1);
	ECL_IO_OUT(2) = ENCODED_TRIG(2);
	ECL_IO_OUT(3) = ENCODED_TRIG(3);
	ECL_IO_OUT(4) = ENCODED_TRIG(4);

	/* 12.5 MHz Pulser (common clock) */
	period(3) = 80 ns;
	GATE_DELAY(2) = PULSER(3);
	stretch(2) = 10 ns; /* 10 ns = 50% duty cycle */
	LEMO_OUT(1) = GATE_DELAY(2);


	/* 10 Hz Pulser (for minimum trigger rate) */
	period(4) = 100 ms;
	GATE_DELAY(3) = PULSER(4);
	stretch(3) = 1 us; 
	LEMO_OUT(2) = GATE_DELAY(3);

	/* Trigger setup */
	tpat_trig(1) = 1;
	tpat_enable = 1;
	trig_stretch(1) = 100 ns;

	/* Master start generation */
	fast_busy_len = 1000ns;
	accept_window_len = 100 ns;
	sum_out_stretch = 100 ns;
	sum_out_mask = ECL_OUT(1), ECL_OUT(2), ECL_OUT(3), ECL_OUT(4), ECL_OUT(5);

	/* Serial timestamp sender */
	SERIAL_TSTAMP_IN = SERIAL_TSTAMP_OUT;
	SERIAL_TSTAMP_LATCH = ACCEPT_PULSE;
	slew_counter_add = 0x1000000; /* in 16 clock cycles */
	slew_counter_add = 0xa00000; /* in ns */
	ECL_OUT(16) = SERIAL_TSTAMP_OUT;

	/* Send Heimtime */
	ECL_OUT(15) = HEIMTIME_OUT;
}


SECTION(auto_bank_switch)
{
	/*
	 * For automatic bank switching, one needs to connect UO to UI.
	 * One may consider using an edge to pulse conversion here.
	 * On UO, the addr threshold flag is transmitted.
	 * A signal on UI triggers a bank switch in the module.
	 */
	ECL_OUT(10) = ECL_IN(2);

	/*
	 * Produce an OR of the inputs.
	 */
	all_or_mask(1) = ECL_IN(2);

	/*
	 * And use the inputs as trigger.
	 */
	TRIG_PENDING[1] = ALL_OR(1);
	TRIG_LMU_OUT(1) = TRIG_LMU_AUX(1);

	/*
	 * In automatic mode we cannot have so high trigger rates
	 * coming in. The second bank must not fill up before we've
	 * read out the first.
	 */
	/* Pulser 1 */
	period(1) = 10 us;
	/* Pulser 2 */
	period(2) = 100 us;

	GATE_DELAY(1) = PULSER(2);
	stretch(1) = 1000 ns;

	/*
	 * Send pulsers to module.
	 */
	ECL_OUT(11) = GATE_DELAY(1);
	ECL_OUT(12) = GATE_DELAY(1);
}