<span style="font-family:arial, sans-serif;font-size:13px;border-collapse:collapse"><span style="font-family:arial, sans-serif;font-size:13px;border-collapse:collapse"><span style="font-family:arial, sans-serif;font-size:13px;border-collapse:collapse"><p style="margin-bottom:12pt;text-align:justify">

<span style="font-size:32pt;font-family:Arial">IEEE International High Level Design </span><span style="font-size:32pt;font-family:&#39;MS Mincho&#39;"></span><span style="font-size:32pt;font-family:Arial">Validation and Test Workshop 2010</span><span style="font-size:13pt;font-family:Arial"></span></p>

<p style="margin-bottom:12pt;text-align:justify"><span style="font-size:13pt;font-family:Arial"> </span></p><p style="margin-bottom:12pt;text-align:justify"><b><span style="font-size:21pt;font-family:Arial">June11-12, 2010</span></b><span style="font-size:13pt;font-family:Arial"></span></p>

<p style="margin-bottom:12pt;text-align:justify"><b><span style="font-size:21pt;font-family:Arial">Anaheim Convention Center (co-located with DAC2010)</span></b><span style="font-size:13pt;font-family:Arial"></span></p>
<p style="margin-bottom:12pt;text-align:justify"><span style="font-size:16pt;font-family:Arial">Register at </span><a href="http://www.hldvt.com/10/registration.html" style="color:rgb(42, 93, 176)" target="_blank"><span style="font-size:16pt;font-family:Arial;color:rgb(0, 0, 153)">http://www.hldvt.com/10/registration.html</span></a> <span style="font-size:16pt;font-family:Arial">by May<b> 17</b></span><span style="font-size:16pt;font-family:Arial"> to receive discounted registration rates. Also book your hotel room at discounted rates by May <span style="font-family:arial, sans-serif;font-size:13px"><span style="font-size:16pt;font-family:Arial"><b>20</b></span><b><sup><span style="font-size:8.5pt;font-family:Arial"><span style="font-size:21px;font-weight:normal">.</span></span></sup></b></span></span></p>

<p style="margin-bottom:12pt;text-align:justify"><span style="font-size:13pt;font-family:Arial"></span></p><p style="margin-bottom:12pt;text-align:justify"><span style="font-family:&#39;Times New Roman&#39;"> </span></p>

<p style="margin-bottom:12pt;text-align:justify"><span style="font-size:16pt;font-family:Arial"><span style="background-repeat:initial;background-color:rgb(255, 255, 204)">For</span> the past 14 years, IEEE International High Level Design Validation and Test Workshop has been a platform <span style="background-repeat:initial;background-color:rgb(255, 255, 204)">for </span>addressing emerging challenges in verification and test methodologies <span style="background-repeat:initial;background-color:rgb(255, 255, 204)">for</span> ICs and systems. </span><span style="font-size:16pt;font-family:Arial">The workshop is an informal forum where EDA tool developers, academics, and industrial practitioners get together to discuss contemporary issues in </span><span style="font-size:16pt;font-family:Arial">verification, debug, synthesis, and test.</span><span style="font-size:13pt;font-family:Arial"></span></p>

<p style="margin-bottom:12pt;text-align:justify"><span style="font-size:16pt;font-family:Arial"> </span><b><span style="font-size:21pt;font-family:Arial">This year&#39;s program will feature….</span></b></p>
<p style="margin-left:29pt;text-align:justify"><span style="font-size:16pt;font-family:Symbol"><span>·<span>    </span></span></span><span style="font-size:16pt;font-family:Arial">Five Regular Sessions</span></p>
<p style="margin-left:29pt;text-align:justify"><span style="font-size:16pt;font-family:Symbol"><span>·<span>    </span></span></span><span style="font-size:16pt;font-family:Arial">Panel: <b><i><span style="color:rgb(34, 30, 31)">Clock Domain Verification Challenges: <span style="font-weight:normal">What experts say?</span></span></i></b></span></p>

<p style="margin-left:29pt;text-align:justify"><span style="font-size:16pt;font-family:Symbol"><span>·<span>    Tutorial: <span style="font-family:Arial, sans-serif;color:rgb(34, 30, 31);font-style:italic;font-weight:bold">Concise, precise and powerful: IEEE 1800-2009 SystemVerilog Assertions</span></span></span></span></p>

<p style="margin-left:29pt;text-align:justify"><span style="font-size:16pt;font-family:Symbol"><span><span></span></span></span><span style="font-size:16pt;font-family:Arial"><span style="font-family:Symbol, sans-serif">·<span>    5 </span></span>Special Sessions:</span></p>

<p style="margin-left:29pt;text-align:justify"><font color="#221E1F" size="6"><span style="font-size:21px"><b><i><span style="color:rgb(0, 0, 0);font-size:13px;font-style:normal;font-weight:normal"></span></i></b></span></font></p>

<font color="#221E1F" size="6"><b><i><p style="margin-top:12pt;margin-right:0in;margin-bottom:12pt;margin-left:1.25in;text-align:justify"><span style="font-size:14pt;font-family:Symbol"><span><span style="font-weight:normal">·</span><span><span style="font-weight:normal">   </span>   <i><span style="font-weight:normal">Hardware Dependent Software Validation</span></i></span></span></span></p>

<p style="margin-top:0in;margin-right:0in;margin-bottom:12pt;margin-left:1.25in;text-align:justify"><span style="font-size:14pt;font-family:Symbol"><span><span style="font-weight:normal">·</span><span><span style="font-weight:normal">      Firmware </span></span></span></span><i><span style="font-size:14pt;font-family:Arial;color:rgb(34, 30, 31)"><span style="font-weight:normal">Validation</span></span></i><i><span style="font-weight:normal"><span style="font-size:14pt;font-family:Arial"></span></span></i></p>

<p style="margin-top:0in;margin-right:0in;margin-bottom:12pt;margin-left:1.25in;text-align:justify"><span style="font-size:14pt;font-family:Symbol"><span style="font-weight:normal">·      Accelerators and Emulators</span></span></p>

<p style="margin-top:0in;margin-right:0in;margin-bottom:12pt;margin-left:1.25in;text-align:justify"><span style="font-size:14pt;font-family:Symbol"><span style="font-weight:normal"><span style="font-weight:bold"><span style="font-weight:normal">·</span><span><span style="font-weight:normal">      </span></span></span>Transaction Level Modeling</span></span></p>

<p style="margin-top:0in;margin-right:0in;margin-bottom:12pt;margin-left:1.25in;text-align:justify"><font face="Symbol, sans-serif" size="6"><span style="font-size:19px"><span style="font-weight:normal">·</span><span><span style="font-weight:normal">      Verification Challenges at ESL</span></span></span></font></p>

<p style="margin-top:0in;margin-right:0in;margin-bottom:12pt;margin-left:1.25in;text-align:justify"><font face="Symbol, sans-serif" size="6"><span style="font-size:19px;font-weight:normal"><br></span></font></p>
</i></b></font></span></span><p style="margin-bottom:12pt;text-align:justify"><b><span style="font-size:16pt;font-family:Arial">Helpful Links:</span></b><span style="font-size:13pt;font-family:Arial"></span></p>
<p style="margin-bottom:12pt;text-align:justify"><span style="font-size:16pt;font-family:Arial">Advance Program: </span><a href="http://www.hldvt.com/10/program.pdf" style="color:rgb(42, 93, 176)" target="_blank"><span style="font-size:16pt;font-family:Arial">http://www.hldvt.com/10/program.pdf</span></a><span style="font-size:16pt;font-family:Arial"></span></p>

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